Development of advanced microcontroller bus architecture multiprocessor interface implemented in FGPA for high-speed and low-power consumption processor

Abstract

Due to urgent needs in daily life, our demand for highly complex and sophisticated automatic control systems is becoming inevitable. That was not possible before the advancement of digital and chip technology. However, nowadays, an Application Specific Integrated Circuit (ASIC) and the System-on-Chip (SoC) have made it much easier to build and control what are usually sophisticated and highly complex systems. ASIC and SoC comprise Very Large-Scale Integrated Circuit (VLSI) chips managed by a digital processor to convert application requirements into hardware operations. However, System-on-Chip (SoC) design faces several major challenges, with power consumption, design verification, and time-to-market pressure among the most pressing. Other key concerns include the growing complexity of designs and the need to effectively manage power delivery. The processor uses a hardware block that provides an interface to access targeted areas within the system using a dedicated bus protocol. Chip complexity, processing speed, power consumption, and chip size issues multiply when meeting these demands. Therefore, a single processor is insufficient for fast and more complex system applications. As a result, a new approach to multiprocessor access systems has emerged in chip manufacturing industries, solving these problems. The actual collective solutions are challenging for researchers and engineers. This research proposes and develops an efficient multiprocessor interface with a sophisticated arbitration scheme to address multiple processor access with higher speed, lower power and lower area to support efficient access by several processors in a system. Instead of typically using one type of arbitration for different processors, this research developed a dual-mode arbitration scheme for multiprocessor access to the system chip to support a broader range of system requirements. This dual-mode arbitration scheme manages access to shared resources such as the bus or memory in a system. Considering the design and fabrication complexity of multiprocessor interface hardware development, this study adopts a hierarchical development approach using the industry-standard Advanced Microcontroller BUS Architecture (AMBA) bus protocol, which is a highly accepted processing technique in the high-tech chip manufacturing industry. The research work is hardware modeled using the Verilog Hardware Description Language (HDL), and its performance is verified using Cadence and the ModelSim simulators; these tools offer comprehensive simulation and verification capabilities, reducing the need for costly physical prototypes and accelerating the design process. It is synthesized and implemented hardware using the Xilinx Synthesis Tool (XST), Electronic Design Automation (EDA) tool suite and Field Programmable Gate Array (FPGA) devices, a widely accepted alternative to synthesizing via custom fabrication in a foundry using Cadence synthesis tools and hardware implementations. Emulation, synthesis, hardware verification, and simulation clearly show that the design hardware achieves a 120% faster, 80% lower power, and 70% less area-efficient interface for multiprocessor access with an intelligent arbitration system. Therefore, for better throughput and faster data transfer, the results of this study can provide a smart solution of an integrated system for bulk data transfer that can be modeled as separate hardware for future work that can be combined or used as a separate intellectual property (IP), or can be done by a Macroblock in the hardware systems. These will encourage future researchers and entrepreneurs in the VLSI chip manufacturing industry.