Publication:
A new carbon nanotube model for high performance logic gates circuit

dc.contributor.affiliation#PLACEHOLDER_PARENT_METADATA_VALUE#en_US
dc.contributor.authorFarhana, Sohelien_US
dc.date.accessioned2024-10-07T03:03:31Z
dc.date.available2024-10-07T03:03:31Z
dc.date.issued2016
dc.description.abstractAggressive scaling of complementary metal oxide semiconductor (CMOS) has led to higher and higher integration density, the higher performance of devices, low power consumption and more complex function. However, it will eventually reach its limit to nanoscale size in near future. As device sizes approach the nanoscale, new opportunities arise from harnessing the physical properties at the nanoscale. Carbon Nanotubes are considered as the most promising carbon nanostructure material for nanoscale electronic device. In this research, a new model of carbon nanotube field-effect transistors (CNTFET) is proposed to design logic gate circuit. In this work, simulation approaches of tight binding method and density of states (DOS) of CNT have been developed and to explore device engineering issues for better transistor performance. By analyzing the electronic properties of CNT including energy dispersion relation, effective mass, doping, carrier concentration and temperature dependent bandgap, an optimum CNT has been considered in this research. An analytical current transport model has been developed to design a better performance CNTFET by analyzing charge, surface potential of the model. By using non equilibrium green function (NEGF) formulation, a better drain current has been achieved from the proposed CNTFET model. Finally a CNTFET model has been designed by using the analytical model parameter. From the details analysis of the device physics, CNT diameter is 1.95 nm and small band-gap is 0.44 eV have been achieved from the graphene's chirality of (25, 0). From analytical model, drain current 69 µA, sub threshold swing (SS) 68mV/decade and drain induced barrier lowering (DIBL) 53.19mV/decade have been found with the channel length of 14 nano meter (nm) CNTFET. Current gain 45 dB, frequency 10 THz have been achieved from the simulation of the model by using 1.8 mS CNTFET transconductance. The logic gate circuit has been developed by using new model of CNTFET. Delay, power, power delay product (PDP), leakage current and frequency response have been simulated and compared.en_US
dc.description.callnumbert TA 418.9 N35 F223N 2016en_US
dc.description.degreelevelDoctoral
dc.description.identifierThesis : A new carbon nanotube model for high performance logic gates circuit /by Soheli Farhanaen_US
dc.description.identityt11100344079SoheliFarhanaen_US
dc.description.kulliyahKulliyyah of Engineeringen_US
dc.description.notesThesis (Ph.D)--International Islamic University Malaysia, 2016en_US
dc.description.physicaldescriptionxviii, 221 leaves : ill. ; 30cm.en_US
dc.description.programmeDoctor of Philosophy in Engineeringen_US
dc.identifier.urihttps://studentrepo.iium.edu.my/handle/123456789/3033
dc.identifier.urlhttps://lib.iium.edu.my/mom/services/mom/document/getFile/pQAWcF02XV3GNxRQl6ndDBQ32lRKy9k020160829160917020
dc.language.isoenen_US
dc.publisherKuala Lumpur: International Islamic University Malaysia , 2016en_US
dc.rightsCopyright International Islamic University Malaysia
dc.subject.lcshCarbon nanotubes -- Researchen_US
dc.subject.lcshNanoelectronicsen_US
dc.titleA new carbon nanotube model for high performance logic gates circuiten_US
dc.typeDoctoral Thesisen_US
dspace.entity.typePublication

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