Browsing by Author "Farhana, Soheli"

Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high wiring complexity is increased packing complexity with increased number of pins. Therefore, high density layout must be used for data bus both in the silicon and on the printed circuit board. Second implication is increased cross-talk noise which is one of the limiting factors in design of high-speed and sophisticated ICs, especially in a low-power voltage environment and high-speed chips for arithmetic applications. Alternate approaches for design of integrated circuits for arithmetic operations that would use standard complementary metal oxide semiconductor (CMOS) technology and address the above issues have been proposed. One possible solution of high wiring complexity, without affecting performance of a chip, is injecting more than two levels of signals into a wire. This is known as multiple-valued logic (MVL), however, due to narrow voltage margins, especially in low power designs, current is proposed as a better approach to MVL design. MVL has been studied extensively due to its potential advantages in chips performing arithmetic intensive operations. A higher radix (radix-4) MVL ADC has been proposed to reduce circuit complexity, size and power. The circuits operation and functionality is verified by using Orchad PSpice 16.0 based on CMOS BSIM V3 0.13?m process parameters. It is found that the circuit can generate up to 256 bit with code width 62.5nA and sampling rate of 500 kHz. The proposed circuit also consumed less power (197?W) compared to others. The circuit is less complexity and performance is compared to others. Hence, the proposed ADC design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on MVL design.

Aggressive scaling of complementary metal oxide semiconductor (CMOS) has led to higher and higher integration density, the higher performance of devices, low power consumption and more complex function. However, it will eventually reach its limit to nanoscale size in near future. As device sizes approach the nanoscale, new opportunities arise from harnessing the physical properties at the nanoscale. Carbon Nanotubes are considered as the most promising carbon nanostructure material for nanoscale electronic device. In this research, a new model of carbon nanotube field-effect transistors (CNTFET) is proposed to design logic gate circuit. In this work, simulation approaches of tight binding method and density of states (DOS) of CNT have been developed and to explore device engineering issues for better transistor performance. By analyzing the electronic properties of CNT including energy dispersion relation, effective mass, doping, carrier concentration and temperature dependent bandgap, an optimum CNT has been considered in this research. An analytical current transport model has been developed to design a better performance CNTFET by analyzing charge, surface potential of the model. By using non equilibrium green function (NEGF) formulation, a better drain current has been achieved from the proposed CNTFET model. Finally a CNTFET model has been designed by using the analytical model parameter. From the details analysis of the device physics, CNT diameter is 1.95 nm and small band-gap is 0.44 eV have been achieved from the graphene's chirality of (25, 0). From analytical model, drain current 69 µA, sub threshold swing (SS) 68mV/decade and drain induced barrier lowering (DIBL) 53.19mV/decade have been found with the channel length of 14 nano meter (nm) CNTFET. Current gain 45 dB, frequency 10 THz have been achieved from the simulation of the model by using 1.8 mS CNTFET transconductance. The logic gate circuit has been developed by using new model of CNTFET. Delay, power, power delay product (PDP), leakage current and frequency response have been simulated and compared.