Publication: Architecture and network-on-chip implementation of a new hierarchical interconnection network
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Subject LCSH
Computer networks
Subject ICSI
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Abstract
Interconnection network is an important issue for massively parallel computer due to the increasing capability and smaller size of the processing elements. In this thesis, we propose a new hierarchical interconnection network called Midimew-connected Mesh Network (MMN) for massively parallel computer. The proposed network consists of multiple basic modules which are 2-D mesh (2m×2m) network and are hierarchically interconnected by a 2-D midimew (2m×2m) network to build the higher levels. Hence, we call it Midimew-connected Mesh Network (MMN). Architectural details, address-ing of nodes, and routing of message of MMN are discussed in details. We have ex-plored various aspects such as network degree, diameter, cost, average distance, bisec-tion width, wiring complexity of the MMN and compared them with other networks. It is shown that the MMN possesses several attractive features, including constant de-gree, small diameter, low cost, small average distance, moderate bisection width, and high fault tolerant performance than that of other conventional and hierarchical inter-connection networks. Network-on-Chip (NoC) addresses the implementability of in-terconnection network on a single chip. We have examined the NoC implementation of MMN. The result shows that, a Level-3 MMN can be laid on a VLSI surface with 4 layers only. We have considered no jump crossing links method to determine the number of layers of MMN.